| 1. |
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mtGEMM: An Efficient GEMM Library for Modern Multi-Core DSPs (IEEE Transactions on Parallel and Distributed Systems) |
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Apr 1, 2026 by Jianbin Fang, Kainan Yu, Peng Zhang, Dezun Dong +4 more
| discuss | doi src S2, crossref
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| 2. |
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VMXDOTP: A RISC-V Vector ISA Extension for Efficient Microscaling (MX) Format Acceleration |
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Mar 5, 2026 by Max Wipfli, Gamze .Islamouglu, Navaneeth Kunhi Purayil, Angelo Garofalo +1 more
| discuss src S2
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| 3. |
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Practicality of MAGIC NOR in a 1T1M Crossbar Array for In-memory Computing (Journal of Circuits, Systems and Computers) |
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Mar 5, 2026 by F. Lalchhandama, Kamalika Datta, Rolf Drechsler, Sandip Chakraborty +1 more
| discuss | doi src S2, crossref
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| 4. |
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Joint Hardware-Workload Co-Optimization for In-Memory Computing Accelerators |
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Mar 4, 2026 by O. Krestinskaya, M. E. Fouda, A. Eltawil, Khaled N. Salama
| discuss src S2
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| 5. |
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Variable Bit-Width All-Optical Content-Addressable Memory Enabled by Sb2Se3 for Similarity Search (Photonics) |
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Mar 3, 2026 by Yi Guo, Xinmeng Hao, Yibo Zhang, Guangsong Yuan +4 more
| discuss | doi src S2, crossref
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| 6. |
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Heterogeneously integrated IGZTO-CMOS neuromorphic CIM achieving 34.8 TOPS/W and 87.7-fJ write energy (Japanese Journal of Applied Physics) |
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Mar 2, 2026 by zhaolong He, Kaichang Chen, Hanfeng Wang, Yaolei Guo +6 more
| discuss | doi src S2, crossref
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| 7. |
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A 319.3-TOPS/W high-efficient computing-in-memory engine with 55nm high-density multi-level NOR-flash array and event-driven neuromorphic architecture (Japanese Journal of Applied Physics) |
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Mar 2, 2026 by Yue Cheng, Yaolei Guo, Hanfeng Wang, zhaolong He +6 more
| discuss | doi src S2, crossref
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| 8. |
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Self-Calibrating Analog Circuitry for Softmax-Scaled Function With Analog Computing-In-Memory (IEEE Transactions on Very Large Scale Integration (VLSI) Systems) |
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Mar 1, 2026 by Linjun Jiang, Yitong Zhou, He Zhang, Wang Kang
| discuss | doi src S2, crossref
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| 9. |
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Reconfigurable FPU With Precision Auto-Tuning for Next-Generation Transprecision Computing (IEEE Transactions on Circuits and Systems Part 1: Regular Papers) |
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Mar 1, 2026 by Guilherme Dias, Luís Crespo, Timo Schlachter, M. A. Heller +4 more
| discuss | doi src S2, crossref
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| 10. |
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Implementation of Boolean Logic Operation in Embedded Flash Memory for In-Memory Computing Applications (IEEE Transactions on Electron Devices) |
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Mar 1, 2026 by Jinhyeok Kim, Sung Jin Bang, Min Sung Kim, Minsuk Koo +1 more
| discuss | doi src S2, crossref
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| 11. |
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End-to-End Design Flow for Resistive Neural Accelerators (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems) |
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Mar 1, 2026 by Max Uhlmann, T. Rizzi, J. Wen, E. Quesada +7 more
| discuss | doi src S2, crossref, openalex
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| 12. |
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A T8T-SRAM Computing-in-Memory Macro for Ternary Deep Neural Networks and Boolean Logic Computations (IEEE Transactions on Very Large Scale Integration (VLSI) Systems) |
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Mar 1, 2026 by Chenghu Dai, Jianhao Zhang, Zihua Ren, Lian Liu +6 more
| discuss | doi src S2, crossref
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| 13. |
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A 40 nm Buffer-Free 7T-SRAM Analog Charge-Domain CIM Macro With Merging Timing Based On Time-Row Division Strategy (IEEE Transactions on Very Large Scale Integration (VLSI) Systems) |
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Mar 1, 2026 by Linjun Jiang, Jianxin Wu, Sifan Sun, Changyu Li +2 more
| discuss | doi src S2, crossref
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| 14. |
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A 28 nm 1.3 TFLOPS/mm2 Floating-Point SRAM-Based CIM Macro With Asynchronous Normalization and Parallel Sorting Alignment for AI-Edge Chip (IEEE Transactions on Very Large Scale Integration (VLSI) Systems) |
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Mar 1, 2026 by Zhiting Lin, Miao Long, Yang Yang, Xin Wang +6 more
| discuss | doi src S2, crossref
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| 15. |
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Latency and Resource Trade-off Analysis of AXI-DMA and BRAM Integration Approaches on SoC-FPGA (Firat University Journal of Experimental and Computational Engineering) |
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Feb 28, 2026 by G. Tatar
| discuss | doi src S2, crossref
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| 16. |
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FPGA-Based Implementation and Software Verification of a 3×3 Convolution Core for Edge AI Systems (Science and Technology of Engineering, Chemistry and Environmental Protection) |
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Feb 28, 2026 by Hanwen Zhang
| discuss | doi src S2, crossref
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| 17. |
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A Highly-Parallel AI Accelerator Architecture for Convolution and Activation, Implemented in Verilog (Science and Technology of Engineering, Chemistry and Environmental Protection) |
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Feb 28, 2026 by Qilin Xie, Jingyu Zhang
| discuss | doi src S2, crossref
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| 18. |
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A FORTIFIED FOURTEEN-TRANSISTOR STATIC MEMORY CELL WITH ENHANCED RESISTANCE TO RADIATION-INDUCED PERTURBATIONS (International Journal of Data Science and IoT Management System) |
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Feb 28, 2026 by G. Kumar, C. Manoj, Bezawada Siva Ganesh, Veeranki Sasidhar +2 more
| discuss | doi src S2, crossref
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| 19. |
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Shifting in-DRAM |
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Feb 27, 2026 by William C. Tegge, Alex K. Jones
| discuss src S2
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| 20. |
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Optimized fault-tolerant data processing module for high-reliability CNN accelerator. (PLoS ONE) |
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Feb 27, 2026 by Sungkwang Yoon, Seung-Han Lee, Juhyeong Jo, Young-woo Lee
| discuss | doi src S2, crossref
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| 21. |
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Multi-Bit Floating-Gate Memory with an Ultrawide Programmable Window. (Small) |
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Feb 27, 2026 by Ce Li, Ning Lin, Dongliang Yang, Tianze Yu +3 more
| discuss | doi src S2
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| 22. |
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GenDRAM:Hardware-Software Co-Design of General Platform in DRAM |
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Feb 27, 2026 by Tsung-Han Lu, Weihong Xu, T. Rosing
| discuss src S2
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| 23. |
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A methodology for accurate benchmarking of neural network accelerators using a high-level synthesis-based hardware generator. (Philosophical transactions. Series A, Mathematical, physical, and engineering sciences) |
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Feb 26, 2026 by Kartik Prabhu, Jeffrey Yu, X. Pan, Priyanka Raina
| discuss | doi src S2, crossref
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| 24. |
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TOM: A Ternary Read-only Memory Accelerator for LLM-powered Edge Intelligence |
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Feb 24, 2026 by Hongyi Guan, Yijia Zhang, Wenqiang Wang, Yizhao Gao +3 more
| discuss src S2
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| 25. |
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S-TRAC: An Algorithm–Hardware Co-design of Sparsity-aware Threshold Adjustment for Accelerator-based RISC-V ISA Extensions (ACM Transactions on Parallel Computing) |
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Feb 24, 2026 by Yueting Li, Terry Tao Ye, Wanshuang Lin, Wendong Xu +2 more
| discuss | doi src S2, crossref
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| 26. |
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Heterogeneous Memory Design Exploration for AI Accelerators with a Gain Cell Memory Compiler |
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Feb 24, 2026 by Xinxin Wang, Lixian Yan, Shuhan Liu, Luke R. Upton +9 more
| discuss src S2
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| 27. |
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Oxide semiconductor gain cell-embedded memory: materials and integration strategies for next generation on-chip memory (Communications Engineer) |
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Feb 23, 2026 by Sang Won Chung, S. Yoon, J. Jeong
| discuss | doi src S2, crossref, openalex
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| 28. |
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A Logic-Reuse Approach to Nibble-based Multiplier Design for Low Power Vector Computing |
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Feb 22, 2026 by Md. Rownak Hossain Chowdhury, Mostafizur Rahman
| discuss src S2
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| 29. |
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TeLLMe: An Efficient End-to-End Ternary LLM Prefill and Decode Accelerator with Table-Lookup Matmul on Edge FPGAs (Symposium on Field Programmable Gate Arrays) |
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Feb 21, 2026 by Ye Qiao, Zhiheng Chen, Yifan Zhang, Yian Wang +1 more
| discuss | doi src S2, crossref
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| 30. |
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FARE: A Fine-grained Pipelined Reconfigurable FlashAttention Kernel (Symposium on Field Programmable Gate Arrays) |
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Feb 21, 2026 by Kaushikkumar S. Rathva, A. Alam, S. Srinivasan, S. K. Mandal
| discuss | doi src S2, crossref
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