A T8T-SRAM Computing-in-Memory Macro for Ternary Deep Neural Networks and Boolean Logic Computations

Mar 1, 2026 by Chenghu Dai, Jianhao Zhang, Zihua Ren, Lian Liu, Lei Meng, Chaoyi Wang, Chunyu Peng, Wenjuan Lu, Zhiting Lin, Xiulong Wu (IEEE Transactions on Very Large Scale Integration (VLSI) Systems)

DOI 10.1109/TVLSI.2025.3650162

We built a T8T-SRAM CIM macro that natively handles ternary activations and weights and doubles as a Boolean-logic engine, using a separated read/write bitcell to dodge read-disturb and clever redundant-row tricks to avoid extra reference circuitry. In 28 nm the macro delivers quantized MACs via an embedded column ADC with activation refresh, showing strong MAC linearity, real logic ops, ultra-high TOPS/W density, and ResNet-18 accuracy parity on MNIST/CIFAR-10 with ternary networks.

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