A Logic-Reuse Approach to Nibble-based Multiplier Design for Low Power Vector Computing

Feb 22, 2026 by Md. Rownak Hossain Chowdhury, Mostafizur Rahman

We recast multiplication as reusable nibble-level precomputation and show a compact shift-add datapath that finishes 8-bit multiplies in two cycles with a short critical path, letting vector lanes scale with far lower area and energy than shift-add or LUT arrays. If you care about practical, low-power AI datapaths, this logic-reuse nibble multiplier gives almost 2x area and power wins in 28 nm while keeping deterministic latency and simple, regular accumulation.

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