S-TRAC: An Algorithm–Hardware Co-design of Sparsity-aware Threshold Adjustment for Accelerator-based RISC-V ISA Extensions

Feb 24, 2026 by Yueting Li, Terry Tao Ye, Wanshuang Lin, Wendong Xu, Ngai Wong, Weisheng Zhao (ACM Transactions on Parallel Computing)

DOI 10.1145/3799240

We built S-TRAC, an algorithm–hardware co-design that tunes sparsity thresholds on the fly and exposes a static sparse-dense format plus dynamic bit-skipping to an accelerator-friendly RISC-V ISA extension, letting the chip skip non-contributing work without losing weight precision. The result is a column-wise LUT shift-accumulate engine and global partial-sum flow that cranks up effective sparsity and collapses memory and energy costs — think 10s× real efficiency gains from smart thresholding, not brute force pruning.

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