Optimized fault-tolerant data processing module for high-reliability CNN accelerator.

Feb 27, 2026 by Sungkwang Yoon, Seung-Han Lee, Juhyeong Jo, Young-woo Lee (PLoS ONE)

DOI 10.1371/journal.pone.0337338

We built a compact PE module that fuses local binary patterns and min-max ops to shrink area and power while reusing the same logic for on-the-fly fault detection, then route around bad PEs for robust systolic-array CNN inference. Synthesized on 45 nm and prototyped on FPGA, it cuts area and dynamic power substantially and boosts fault resilience with >94% test coverage and meaningful error reduction.

source S2, crossref