FPGA-Based Implementation and Software Verification of a 3×3 Convolution Core for Edge AI Systems

Feb 28, 2026 by Hanwen Zhang (Science and Technology of Engineering, Chemistry and Environmental Protection)

DOI 10.61173/des73n80

We built a compact 3×3 convolution core in Verilog and proved bit-accurate equivalence to a Python/NumPy fixed-point model using Vivado exports, enabling full HW–SW coverification without ever touching an FPGA board. This reproducible, boardless workflow slashes prototyping time for edge-AI convolution accelerators and gives a solid baseline for scaling FPGA-based inference in constrained embedded systems.

source S2, crossref