A 319.3-TOPS/W high-efficient computing-in-memory engine with 55nm high-density multi-level NOR-flash array and event-driven neuromorphic architecture

Mar 2, 2026 by Yue Cheng, Yaolei Guo, Hanfeng Wang, zhaolong He, Chenhao Tang, Xinjian Wang, Jingyao Chi, Dawei Gao, Dianyu Qi, Yitao Ma (Japanese Journal of Applied Physics)

DOI 10.35848/1347-4065/ae4be6

We built a computing-in-memory spiking accelerator using a dense 55nm 1.5T multi-level NOR flash array to store tunable synapses and drive event-driven SNN inference, achieving crazy energy efficiency (319.3 TOPS/W) and tiny update costs compared to SRAM/RRAM designs. It’s basically a high-density, low-power edge SNN engine that folds nonvolatile multi-level NOR into massively parallel spike accumulation and neuron firing circuits for real-time, on-device sensing.

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