A 40 nm Buffer-Free 7T-SRAM Analog Charge-Domain CIM Macro With Merging Timing Based On Time-Row Division Strategy

Mar 1, 2026 by Linjun Jiang, Jianxin Wu, Sifan Sun, Changyu Li, Wang Kang, He Zhang (IEEE Transactions on Very Large Scale Integration (VLSI) Systems)

DOI 10.1109/TVLSI.2026.3656426

Built a buffer-free 7T SRAM charge-domain CIM macro in 40 nm that packs a compact bitcell, a configurable input unit, a time-row division scheme to tame negative voltage swings, and a clever merging timing that hides the input phase so compute and input overlap—resulting in a 512Kb macro with high density and 4-bit energy efficiency up to 290 Tops/W. This is a pragmatic take on analog SRAM CIM that prioritizes real-time throughput and area efficiency without extra buffering or bulky multiply hardware.

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