End-to-End Design Flow for Resistive Neural Accelerators

Mar 1, 2026 by Max Uhlmann, T. Rizzi, J. Wen, E. Quesada, B. Beattie, Karlheinz Ochs, E. Pérez, P. Ostrovskyy, C. Carta, Christian Wenger, Gerhard Kahmen (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems)

DOI 10.1109/TCAD.2025.3597237

We built a complete end-to-end design and verification flow for RRAM-based neural accelerators using a LUT-based Verilog-A 1T1R model and a Python wrapper to bridge PyTorch ANNs with circuit-level simulation, then pushed the last layer of MNIST and CIFAR-10 networks through schematic and layout-extracted SPICE to show how conductance spacing and device variability change accuracy. If you care about realistic hardware tradeoffs instead of idealized software nets, this flow makes it dead simple to quantify how device physics and variability actually bite your network.

source S2, crossref, openalex