A PN-Free Digital 3-SAT Accelerator Using Crossbar Architecture and Frequency-Controlled Counters

Jan 31, 2026 by Zhezheng Ren, Chenao Yuan, Yuke Zhang, Shiyu Su (International Symposium on High-Performance Computer Architecture)

DOI 10.1109/HPCA68181.2026.11408459

We built a fully digital, PN-free 3-SAT accelerator that trades analog noise and RNGs for frequency-controlled counters as oscillators and a polynomial clause-to-variable feedback loop, yielding intrinsic stochasticity and a standard-cell, synthesizable crossbar you can tape out in mainstream CMOS. Implemented on FPGA and 12/22/65 nm ASICs, it’s the first digital 3-SAT engine to hit 250 variables with 100% solvability and beats prior silicon on speed and scalability.

source S2, crossref