NPUWattch: ML-Based Power, Area, and Timing Modeling for Neural Accelerators

Jan 31, 2026 by Sehyeon Kim, Minkwan Kim, Chanho Park, Hanmok Park, Seonghoon Kim, Taigon Song, William J. Song (International Symposium on High-Performance Computer Architecture)

DOI 10.1109/HPCA68181.2026.11408488

We built NPUWattch, an ML-powered PAT modeling framework that learns nonlinear technology and design scaling from unified 65 nm-to-2 nm post-layout logic and SRAM datasets, so you can get accurate pre-silicon power, area, and timing for neural accelerators without the brittle assumptions of old table-based models. It’s fun because the model actually generalizes across tech nodes and weird corner cases—validated on many open-source NPUs with just 2.7% average error.

source S2, crossref