A Comprehensive Survey of Custom Layout Techniques for 6T, 8T, and 10T SRAM Bitcells Across Planar CMOS and FinFET Technology Nodes

Jan 1, 2026 by Ravi S. Siddanath, Sukhen Mondal, Manish Goswami, Kavindra Kandpal (IEEE Access)

DOI 10.1109/ACCESS.2026.3664102

We pulled together hands‑on custom layout tricks for 6T, 8T and 10T SRAM cells targeting both UMC 28 nm planar and GPDK 18 nm FinFET so you can actually build, compare and iterate bitcells without relying on foundry black‑box IP. If you care about squeezing area, boosting read stability or taming leakage across process nodes, this survey gives practical layout patterns and node‑specific tradeoffs that make experimenting with new SRAM topologies way less painful.

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