Power-Optimized ALU Framework Based on Pseudo Dynamic Buffer Domino Logic

Jan 22, 2026 by C. Reddy, Surekha R Sakhare, Yasmeen M S, Ruchitha B L, Sanjana Benkal, Vikas Vardhan S P (2026 International Conference on Intelligent and Innovative Technologies in Computing, Electrical and Electronics (IITCEE))

DOI 10.1109/IITCEE67948.2026.11394168

Built a semi-custom 64-bit ALU using Pseudo Dynamic Buffer domino logic in 90 nm via Cadence Genus to tackle the pesky tradeoff between speed and power; by curbing unnecessary transitions we cut switching energy by ~27% and slashed leakage by ~79%, showing PDB domino is a practical route to much leaner ALUs for low-power processors.

source S2, crossref