Measurement and Analysis of Multistate Ferroelectric Transistors in 28 nm CMOS Process

Jan 1, 2026 by Sayma Nowshin Chowdhury, Alexander L. Mazzoni, Xiaohan Zhang, Andreu L. Glasmann, H. Mulaosmanovic, S. Dünkel, G. Beernink, Sven Beyer, Sina Najmaei, Sahil Shah (IEEE Journal of the Electron Devices Society)

DOI 10.1109/JEDS.2026.3664683

We put real FeFET synapses into a 28 nm GF CMOS flow and showed reliable multi-bit programming and long retention with a simple incremental pulsing scheme, then dug into how device size, read gate bias, and array topology trade off determinism versus density. The punchline: bigger FeFETs make predictable synapses, smaller ones pack more, and choice of 1‑FeFET vs nT–1FeFET arrays fundamentally shifts the density and selectivity trade-offs compared with SRAM—practical guidance for co-designing FeFET arrays in neuromorphic accelerators.

source S2, crossref