Design of Ferroelectric Field-Effect Transistor (FeFET)-Based Computing-in-Memory Architecture with Energy-Efficient and Low Latency for Edge AI Computing

Feb 16, 2026 by Chen He, Wei Li, Jianjun Li, Qiquan Li, Zhiang Xie, Tao Du (Electronics)

DOI 10.3390/electronics15040841

We built an ADC-free CiM architecture using FeFETs to store weights and implement NOR/NAND/XNOR logic in-memory, slashing energy and latency compared with analog CiM while keeping robustness across PVT corners. To show it scales, we extended to 3-bit FeFET-CiM gates and a kNN-specific subtractor that hits sub-100 fJ/OP and sub-ns latency, cutting data movement by 300x for edge AI.

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