High-Speed AXI4-Lite Dynamic MAC Accelerator for RISC-V SoC Designs

Jan 1, 2026 by Thirunaavukarasan S, Sriram N, R. G (ITM Web of Conferences)

DOI 10.1051/itmconf/20268201016

Built a runtime-configurable 8/16/32-bit MAC accelerator with a Radix-4 Booth multiplier and Brent–Kung adder in a two-stage pipeline that keeps latency constant across precisions, connects over AXI4-Lite for register-level control, and runs on FPGAs without any DSP slices. It’s a portable, low-latency way to trade accuracy for energy and area in RISC-V SoCs and edge processors.

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