A Novel SRAM In-Memory Computing Accelerator Design Approach with R2R-Ladder for AI Sensors and Eddy Current Testing

Jan 15, 2026 by K. Becker, Martin Zimmerling, Matthias Landwehr, Dirk Koster, Hans-Georg Herrmann, Wolf-Joachim Fischer (AI Sensors)

This work presents a 6T-SRAM-based in-memory computing (IMC) system fabricated in a 180 nm CMOS technology. A total of 128 integrated polysilicon R2R-DACs for fully analog wordline control and performance analysis are integrated into the system. The proposed architecture enables analog computation directly inside the memory array and introduces a compact 1-bit per-column comparator scheme for energy-efficient classification without requiring ADCs.