A Novel SRAM In-Memory Computing Accelerator Design Approach with R2R-Ladder for AI Sensors and Eddy Current Testing

Jan 15, 2026 by K. Becker, Martin Zimmerling, Matthias Landwehr, Dirk Koster, Hans-Georg Herrmann, Wolf-Joachim Fischer (AI Sensors)

DOI 10.3390/aisens2010002

We built a 6T-SRAM in-memory compute chip in 180 nm that uses 128 on-chip polysilicon R2R DACs for fully analog wordline control and a 1-bit-per-column comparator to do ADC-free, time-encoded inference right inside the memory array — including a sensor front end to classify real eddy current data on-chip. Measured silicon, pull-down-dominant sizing, and an online training loop show this compact IMC approach is practical for low-power AI sensors, packing impressive TOPS/mm2 and bringing adaptable edge ML to non-invasive testing.

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