Accelerating SpMV on HBM-equipped FPGAs: hardware-software co-design and collaboration

Nov 28, 2025 by José Oliver Segura

DOI 10.5821/dissertation-2117-449855

We redesigned SpMV from the ground up for HBM FPGAs: a co‑designed double‑precision accelerator plus a new matrix encoding that maximizes inter/intra‑row pipelined parallelism without memory replication, and a second, highly parametric version that slashes metadata, reclaims zero‑padding, and becomes precision‑agnostic to push arithmetic and energy efficiency well beyond prior FPGA efforts.

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