Azure-Lily: An FPGA Architecture with Analog IMC Engines for Efficient AI

Feb 18, 2026 by Archit Gajjar, R. Sunketa, Lei Zhao, Omar Eldash, Aishwarya Natarajan, Giacomo Pedretti, Aman Arora, Paolo Faraboschi, J. Ignowski, Luca Buonanno (ACM Transactions on Architecture and Code Optimization (TACO))

Modern AI models place heavy demands on compute resources, underscoring the importance of hardware accelerators that can balance performance, energy, and flexibility. The ever-growing demand for AI computing, coupled with slowing performance gains in chip manufacturing, has heightened the role of FPGA-based accelerators due to their rapid adaptability, reprogrammability, and support for custom parallel data flows. In this work, we introduce a domain-optimized FPGA architecture designed for deep neural network (DNN) inference by embedding analog in-memory compute blocks, specifically, RRAM-based Dot Product Engines (DPE), directly into the fabric.