Azure-Lily: An FPGA Architecture with Analog IMC Engines for Efficient AI

Feb 18, 2026 by Archit Gajjar, R. Sunketa, Lei Zhao, Omar Eldash, Aishwarya Natarajan, Giacomo Pedretti, Aman Arora, Paolo Faraboschi, J. Ignowski, Luca Buonanno (ACM Transactions on Architecture and Code Optimization (TACO))

DOI 10.1145/3796723

We built Azure-Lily, an FPGA fabric with RRAM analog in-memory Dot Product Engines embedded into the routing to slash data movement and turbocharge DNN inference — think FPGA flexibility with near-memory analog MACs. Using a 22 nm VTR flow and a custom event-driven simulator, we show massive latency, throughput, and energy gains, making reprogrammable fabrics actually competitive for energy-constrained AI workloads.

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