High-Performance RISC-V CSR Access in FPGAs: Optimized Microarchitecture for Efficient Decoding and Multiplexing

Jan 19, 2026 by Miguel Jiménez Arribas, A. M. Hellín, Manuel Prieto (ACM Transactions on Reconfigurable Technology and Systems)

DOI 10.1145/3787491

We built a hardware-aware CSR subsystem for RISC-V on FPGAs that swaps naive LUT muxing for a heterogeneous mix of BRAM, DSPs, CARRY/LUT fabrics and ft-flops to slash logic depth and boost Fmax; depending on knobs you get 50–300% speedups and the winner hits 250 MHz on Artix-7 while cutting area and dynamic power. It’s a nerdy reminder that low-level, FPGA-native microarchitecture beats pure behavioral descriptions when decoding and multiplexing are the bottleneck.

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