Decomposing Large-Scale Ising Problems on FPGAs: A Hybrid Hardware Approach

Feb 17, 2026 by Ruihong Yin, Yue Zheng, Chaohui Li, A. Efe, Abhimanyu Kumar, Ziqing Zeng, Ulya R. Karpuzcu, S. Sapatnekar, Chris H. Kim

We pushed Ising problem decomposition off the CPU and into an FPGA tightly coupled with our 28nm oscillator-based solver, so the high-speed analog core actually stays fed instead of waiting on preprocessing. The hybrid co-design lets us scale to thousands of variables with minimal host-device latency, nearly 2x end-to-end speedup and >100x energy efficiency gains over tuned CPU baselines.

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