MetaAccel: A High-Performance and Agile Accelerator Design Framework With Multi Clock Domain Optimization for Complex CNN

Feb 1, 2026 by Zhan Li, Yuxian Jiang, Zhihan Zhang, Jiahui Huang, Qunkang Meng, Xingyu Shi, Hao Wang, Qijun Huang, Sheng Chang (IEEE Transactions on Circuits and Systems Part 1: Regular Papers)

DOI 10.1109/TCSI.2025.3586373

We built MetaAccel, a fully pipelined FPGA accelerator that uses two clock domains plus a hyperparameter-driven resource model to squeeze much higher compute and on‑chip memory efficiency out of complex CNNs while keeping design agile; it handles branched/heterogeneous networks with minimal fuss and pushes throughput and DSP efficiency well past prior FPGA work.

source S2, crossref, openalex