Energy-Efficient Edge-AI Accelerator Design Using Reconfigurable FPGA-Based VLSI Architecture

Jan 1, 2025 by M. Kavitha (Journal of VLSI and Embedded System Design)

DOI 10.66054/jvesd/01.01.04

Built a reconfigurable FPGA-centric VLSI accelerator tuned for DNN inference that squeezes energy and latency by marrying a PE array, on-chip data-reuse and configurable dataflows so the same silicon morphs to different CNN workloads; we implemented it in an FPGA flow and show a practical, scalable path to real-time, low-power Edge-AI beyond CPUs/GPUs.

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