Design and Analysis of SIMD Functional Units for RISC-V P-Extension Instructions

Jan 22, 2026 by Nancy Gupta, Gopal R. Raut, D. Selvakumar, Pranose J. Edavoor, Prasoon, Nissy Niharika (2026 International Conference on Intelligent and Innovative Technologies in Computing, Electrical and Electronics (IITCEE))

DOI 10.1109/IITCEE67948.2026.11394668

We built and verified independent p‑SIMD functional units and a hierarchical decoder for RV32/RV64 P‑extension in Verilog, implementing a broad 323‑instruction subset and a pipeline‑friendly front end so they slot into existing cores at the execute stage. Tested with Vivado and QuestaSim plus UVM, these units are meant as drop‑in, high‑performance SIMD building blocks for compute‑heavy edge and embedded RISC‑V designs.

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