Hardware implementation of memristor-based artificial neural networks

Mar 4, 2024 by F. Aguirre, A. Sebastian, M. Le Gallo, Wenhao Song, Tong Wang, J. J. Yang, Wei D. Lu, Meng-Fan Chang, D. Ielmini, Yuch-Chi Yang, Adnan Mehonic, Anthony J. Kenyon, M. A. Villena, J. Roldán, Yuting Wu, Hung-Hsi Hsu, N. Raghavan, J. Suñé, Enrique Miranda, A. Eltawil, G. Setti, Kamilya Smagulova, K. Salama, O. Krestinskaya, Xiaobing Yan, K. Ang, Samarth Jain, Sifan Li, O. Alharbi, S. Pazos, M. Lanza (Nature Communications)

Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel. The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets of data. More recent computing paradigms, such as high parallelization and near-memory computing, help alleviate the data communication bottleneck to some extent, but paradigm- shifting concepts are required.