Implementation of a high-performance multiply-accumulate unit using DRPPE-enhanced vedic multiplier and flag-driven SPS adder

Jan 19, 2026 by Dyana Christilda Varghese, Anselem Benet Raja Y (Engineering Research Express)

DOI 10.1088/2631-8695/ae3a3d

We built a DRPPE-enabled MAC that marries a 16×16 Urdhva-Tiryakbhyam Vedic multiplier with a flag-driven selective partial-sum adder to crush carry propagation and switching activity, yielding sub-2.1 ns critical path and ~465 MHz operation on a Virtex-5 while slashing power and area. It’s a practical, reconfigurable high-throughput MAC for DSP/AI/FPGA stacks that’s all about fast partial-product generation and smart control logic instead of brute-force gates.

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