In-Pipeline Integration of Digital In-Memory-Computing into RISC-V Vector Architecture to Accelerate Deep Learning

Feb 2, 2026 by Tommaso Spagnolo, Cristina Silvano, R. Massa, Filippo Grillotti, T. Boesch, G. Desoli

We stuck a digital in-memory compute tile right into the RISC-V vector pipeline and added four vector-friendly ISA ops so the core can load, compute, and write back without wasting cycles or memory bandwidth — the result is a tiny, practical integration that keeps the DIMC tile fed and delivers massive real-world speedups for ResNet-50 on edge-class silicon. This is not a paper about magical new devices but about the messy engineering of making DIMC actually usable in a RISC-V vector pipeline, with 137 GOP/s peak and order-of-magnitude area-normalized wins while staying within realistic hardware limits.

source S2