Surface-enhanced thermal dissipation in 3D vertical resistive memory arrays with top selector transistors.

Jan 22, 2026 by Arman Kadyrov, Seunghyun Lee, Batyrbek Alimkhanuly, Shubham Patil, Anupom Devnath, Junseong Bae, Minwoo Lee, Jinsu Choi, G. Hwang, Seunghyun Lee (Nanoscale Horizons)

DOI 10.1039/d5nh00653h

We built microfabricated 3D RRAM stacks and showed that putting the selector transistor right at the memory interface dramatically tames nanoscale hotspots during heavy neuromorphic currents — finite-element and device-level models show up to ~11% less local heating and peak temps crashing from >160°C to <60°C within 20 ns across 10–100 layers. This is a practical, layout-level lever for keeping stacked resistive arrays cool and reliable under the brutal current densities neuromorphic workloads demand.

source S2, crossref