Performance investigation of non-volatile memories for energy-efficient on-chip L2 caches

Feb 1, 2026 by Inderjit Singh, Balwinder Raj, Mamta Khosla, Tajinder Kaur (Journal of Electrical Engineering)

DOI 10.2478/jee-2026-0002

We benchmarked STT-, SOT-, VCMA-MRAM and RRAM against SRAM across 16KB–8MB L2 caches at 22 nm and show when NVMs actually win: SRAM still rules tiny caches, but beyond ~128KB SOT-MRAM and aggressive STT-MRAM slash the energy-area-delay tradeoff (up to ~97–98% better at 2MB) while cutting leakage by ~99% for STT-A—RRAM and vanilla STT suffer brutal write-energy penalties, and associativity matters less as caches grow.

source S2, crossref