Scalable and robust multi-bit spintronic synapses for analog in-memory computing

Feb 16, 2026 by K. K. Gupte, Sohan Salahuddin Mugdho, Cheng Huang, Cheng Wang (npj Unconventional Computing)

DOI 10.1038/s44335-026-00055-7

We built an MTJ-based multi-level spintronic synapse by exchange-coupling a standard free layer to a granular magnetic nanostructure, letting the per-grain energy barrier distribution give near-continuous resistive states for robust analog weights. Cross-layer sims and system-level inference runs show this scalable 2-bit-per-cell MRAM scheme slashes hardware cost and variability compared with other multi-level NVMs while keeping accuracy—great for energy-efficient, high-throughput in-memory DNNs.

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